Methods and circuits for decision-feedback equalization using compensated decision regions

ABSTRACT

A decision-feedback equalizer (DFE) samples an input signal with respect to a gamut of p reference-voltage levels to place the symbol represented by the input signal within a voltage region. The DFE derives a set of tentative decisions for the voltage region, the set excluding at least one of the possible values for the symbol under consideration. A feedback stage then selects a final decision from among the tentative decisions.

BACKGROUND

Binary communication systems represent information using just twosymbols—e.g. relatively high and low voltages—to alternatively representa logical one and a logical zero (i.e. 1 or 0). The number of levelsused to represent digital data is not limited to two, however. Forexample, a type of signaling referred to as PAM-4 (for 4-levelpulse-amplitude modulation) provides for four discrete pulse amplitudes(voltages) to convey two binary bits of data per symbol (i.e., 00, 01,10, or 11). A series of symbols can thus be communicated as a voltagesignal that transitions between levels in a manner that reflects theseries. The time each voltage level is held to represent a symbol istermed the “symbol time” and the speed with which symbols can becommunicated is termed the “symbol rate.” A receiver recovers a set ofsymbols from a signal by comparing the voltage during each symbol timeagainst one or more reference-voltage levels to distinguish betweensymbols.

High performance communication channels suffer from many effects thatdegrade symbols, and consequently render them difficult to resolve.Primary among them are frequency dependent channel loss (dispersion) andreflections from impedance discontinuities. These effects causeneighboring symbols (voltage levels) to interfere with one another andare commonly referred to collectively as Inter-Symbol Interference(ISI). For example, neighboring relatively high-voltage symbols mayspread out to raise the level of neighboring lower-voltage symbols; ifthe resulting voltage distortion is sufficiently high, the lower-voltagesymbols may be interpreted incorrectly. Lower-voltage symbols maylikewise induce errors in neighboring higher-voltage symbols.

ISI becomes more pronounced at higher signaling rates, ultimatelydegrading signal quality such that distinctions between originallytransmitted symbols may be lost. Some receivers mitigate the effects ofISI using one or more equalizers. One common type of equalizer, thedecision-feedback equalizer (DFE), corrects for ISI imposed on a currentsymbol by a prior symbol by multiplying the value of the prior symbol bya “tap value” calibrated to account for the ISI and adding the resultantproduct to the voltage level used to interpret the current symbol. ISIfrom a prior symbol that tends to raise (lower) the level of the currentsymbol is thus offset by a similar rise (fall) in the reference againstwhich the current symbol is evaluated. The same principle can beextended to multiple preceding symbols.

In high-speed systems it can be difficult to resolve recently receivedsymbols in time to calculate their impact on incoming symbols and applythe requisite feedback. Symbol pre-decision is used in some DFEs to easethis timing constraint. Each received symbol is ISI-compensated based onhypothetic decision feedback signals and sampled against decisionreference levels to make tentative symbol pre-decisions. The decisionfeedback loop is then used to select among the tentative pre-decisionsafter the prior symbol is resolved.

The use of pre-decisions to delay the need for a final decision on aprior symbol reduces the latency of the decision-feedback loop and helpstiming closure of the timing critical path. Unfortunately, thisadvantage requires increasing the requisite number of samples for eachsymbol, and thus the required circuit area and power. Binary signalingrequires two tentative decisions for each prior symbol underconsideration, one for each of the two possible values of the priorsymbol. PAM-4 signaling doubles the number of possible feedback signalcombinations relative to common binary schemes, which results insignificantly higher power usage and circuit area. PAM-4 also increasesthe number of pre-decisions that require consideration, which makestiming closure more difficult.

BRIEF DESCRIPTION OF THE DRAWINGS

The detailed description is illustrated by way of example, and not byway of limitation, in the figures of the accompanying drawings and inwhich like reference numerals refer to similar elements and in which:

FIG. 1 depicts a PAM-4 DFE 100 that receives an input signal x (lowerleft) distorted by inter-symbol interference (ISI) and expressing aseries of symbols each representing one of four pulse amplitudes(voltages) to convey two binary bits of data per symbol.

FIG. 2 includes an eye diagram 200 and table 205 illustrating how ISIcalibration circuitry 117 of FIG. 1 calculates ISI-adjusted referencelevels V_(p-1):V₀.

FIG. 3 depicts an eye diagram 300 in which ISI-adjustedreference-voltage levels V_(p-1):V₀ of table 205 of FIG. 2 partition theentire range of received signal levels thirteen decision regions R₁₂:R₀.

FIG. 4 depicts a tentative-decision look-up table (LUT) 400 relatingvoltage regions R₁₂:R₀ for a current symbol value d_(n)(k) to tentativesymbol values given a preceding symbol value d_(n-1) (k).

FIG. 5 details one slice 500 of open-loop equalizer 105 of FIG. 1,including first open-loop stage 120(0) and second open-loop stage125(0).

FIG. 6 is a decision tree 600 illustrating the binary search performedby first open-loop stage 120(0) to identify voltage regions R₁₂:R₀ andthe sets of tentative decisions TD₁₂:TD₀ associated with each regionshown in FIG. 3.

FIG. 7 depicts a tentative-decision LUT 700 similar to LUT of FIG. 4 butincluding a mapping of partial region decisions r₀, r₁, r₂, and r₃ tovoltage regions R₁₂:R₀ and tentative-decision sets TD₁₂:TD₀.

FIG. 8A depicts a second open-loop stage 800 in accordance with anotherembodiment.

FIG. 8B illustrates how sub-stage 810 of FIG. 8A shares sets oftentative pre-decisions TD_(q-1):TD₀ from sub-stage 805 to producerefined sets of tentative pre-decisions RTD_(q-1):RTD₀.

DETAILED DESCRIPTION

FIG. 1 depicts a PAM-4 DFE 100 that receives an input signal x (lowerleft) distorted by inter-symbol interference (ISI) and expressing aseries of symbols each representing one of four pulse amplitudes(voltages) to convey two binary bits of data per symbol. DFE 100includes N+1 DFE slices—collectively a “lane”—each operating at a datarate of 1/(N+1) times that of input signal x with a timing offset of onesymbol time of input signal x relative to the neighboring DFE slice. TheN+1 DFE slices thus process input signal x in parallel to relax timingconstraints on DFE 100. In general, input signal x_(n)(k) represents thesample of the nth DFE slice for n=0:N at discrete time k, and outputsignal d_(n)(k) represent the final decision for the sample value of thenth DFE slice for n=0:N at discrete time k. DFE slice 0, for example,samples a symbol of input signal x₀(k) with respect to a gamut of preference-voltage levels V[p−1:0] to place the symbol within a voltageregion R, makes a set of tentative decisions TD indicating the possiblesymbol values represented by the voltage region R, and considers thevalue of a prior symbol d_(N)(k−1) from DFE slice N to narrow thetentative decisions down to a final decision d₀(k). The number of DFEslices is thirty-two (N=31) in one embodiment.

DFE 100 includes an open-loop (feed-forward) equalizer 105 and aclosed-loop (feedback) decision stage 110, each of which is divided intoN+1 slices. A reference block 115 includes ISI calibration circuitry 117that develops p reference-voltage levels Vp−1:V0 and pre-decisioncomputation circuitry 119 that produces q sets of tentativepre-decisions TDq−1:TD0 based on the voltage levels. As detailed below,each set of tentative pre-decisions identifies fewer than four tentativevalues of a sampled symbol given its measured voltage region. Decisionstage 110 thus selects from among fewer than the four potential valuesof a PAM-4 system for each incoming symbol. To save power and area, thereference signals from block 115 are shared by all N DFE slices in thisembodiment.

Open-loop equalizer 105 includes a first open-loop stage 120 and asecond open-loop stage 125, each of which is divided into N+1 slices inservice of like-referenced ones of DFE slices 0 to N. Considering DFEslice 0, first open-loop stage 120(0) samples each symbol in seriessymbols x₀(k) relative to all or a subset of reference-voltage levelsV_(p-1):V₀ to locate the voltage level for the symbol within one of aset of q voltage regions R_(q-1):R₀. Second open-loop stage 125(0)selects one of pre-decision sets TD_(q-1):TD₀ using the identifiedvoltage region.

Tentative-decision sets TD_(q-1):TD₀, also referred to as “pre-decisionsets,” represent the symbol value or values that are possible for agiven voltage region, with each set excluding at least one of the fourPAM-4 values. Each tentative-decision set also relates the possiblevalue or values to the value expressed by the preceding symbol. Decisionstage 110(0) selects a final decision d₀(k) from among the tentativesubset of possible values based on the resolved value of prior decisiond_(N)(k−1) from the DFE slice N charged with resolving the value of thepreceding symbol in overall input signal x. Second open-loop stage125(0) simplifies the process of making the final decision by reducingthe number of possibilities to a tentative subset and thus eases thetiming closure of the closed-loop decision feedback loop of decisionstage 110(0).

FIG. 2 includes an eye diagram 200 and table 205 illustrating how ISIcalibration circuitry 117 of FIG. 1 calculates ISI-adjusted referencelevels V_(p-1):V₀. PAM-4 DFE 100 communicates four symbol values s₃:s₀.In particular, symbol value s₀ is the decision symbol for PAM-4 transmitlevel (−3); symbol value s₁ is the decision symbol for PAM-4 transmitlevel (−1); symbol s₂ is the decision symbol for PAM-4 transmit level(1); and symbol value s₃ is the decision symbol for PAM-4 transmit level(3). These four PAM-4 signal levels are distinguished using threenominal reference-voltage levels. Reference voltage level V_(b) (bottomlevel) represents the decision boundary between symbol values s₀ and s₁;voltage level V_(c) (center level) the decision boundary between symbolvalues s₁ and s₂; and voltage level V_(t) (top level) the decisionboundary between symbol values s₂ and s₃.

Nominal reference levels V_(b), V_(c), and V_(t) are adjusted using DFEtaps to generate 3×2^(2L) ISI-adjusted reference levels, where L is thenumber of DFE taps. DFE 100 of FIG. 1 has one tap, calling for the threesets of four (twelve) reference-voltage levels provided in the followingequations 1-3.

$\begin{matrix}{{\hat{V}}_{t,{m{(0)}},\ldots,{m{({L - 1})}}} = {V_{t} + {\sum\limits_{l = 0}^{L - 1}\;{c_{l}\left\lbrack {m(l)} \right\rbrack}}}} & (1) \\{{\hat{V}}_{c,{m{(0)}},\ldots,{m{({L - 1})}}} = {V_{c} + {\sum\limits_{l = 0}^{L - 1}\;{c_{l}\left\lbrack {m(l)} \right\rbrack}}}} & (2) \\{{\hat{V}}_{b,{m{(0)}},\ldots,{m{({L - 1})}}} = {V_{b} + {\sum\limits_{l = 0}^{L - 1}\;{c_{l}\left\lbrack {m(l)} \right\rbrack}}}} & (3)\end{matrix}$

Vector c_(l)=[−α_(l), −β_(l), β_(l), α_(l)], for l=0:L−1 represents theDFE taps for the cancellation of ISI from the lth post-cursors, andm(l)ϵ{0, 1, 2, 3} is an index for selecting the m(l)th entry in vectorc_(l); α_(l) is the DFE tap to be added to the received signal (orsubtracted from the reference level) for ISI compensation when the lthpost-cursor decision is s₃, for l=0:L−1; and β_(l) is the DFE tap to beadded to the received signal for ISI compensation when the lthpost-cursor decision is s₂, for l=0:L−1.

The ISI-adjusted reference levels are either static or quasi-staticbecause the DFE taps and reference levels are either fixed after initialcalibration or adapted periodically in operation. The computation of theISI-adjusted reference levels can be implemented either as firmware orlow-speed logic for reduced power. The ISI-adjusted reference levels areshared by the parallel DFE slices in a lane.

Given a preceding symbol decision s₀, top reference level Vt is adjustedby subtracting the corresponding DFE tap α₀. The ISI-adjusted referencelevel Vt-α₀ replaces V_(t) as the decision boundary between symbols s₂and s₃. Offsets for top reference-voltage level Vt are similarlycalculated for the three remaining potential symbol decisions, as arethe four offsets for each of center and bottom reference-voltage levelsV_(c) and V_(b). Without loss of generality, table 205 lists theISI-adjusted reference levels for a one-tap PAM-4 DFE that cancels ISIfrom the first post-cursor symbol, previous decision d_(n-1)(k).Calculating tap values is well known to those of skill in the art so adetailed treatment is omitted.

FIG. 3 depicts an eye diagram 300 in which ISI-adjustedreference-voltage levels V_(p-1):V₀ of table 205 of FIG. 2 partition theentire range of received signal levels into thirteen ISI-compensateddecision regions R₁₂:R₀. There are twelve reference-voltage levels andthirteen decision regions in this example but more of fewer can be usedfor PAM-4 or other modulation schemes. In one embodiment selecting avalue of p between eight and the lessor of sixteen or 3×2^(2L), where Lis the number of DFE taps, tends to optimize for power and area.

The highest and lowest regions R₁₂ and R₀ are dispositive as to thesymbol value they represent. Region R₁₂ is above all reference-voltagelevels V₁₁:V₀ and thus represents the highest value s₃. Region R₀ isbelow all reference-voltage levels V₁₁:V₀ and thus represents the lowestvalue s₀. The remaining regions are not dispositive but do exclude atleast one of the four possible symbol values. Voltage region R₈, forexample, is above all possible variants of bottom reference voltageV_(b) (i.e. V₁ to V₄) and thus cannot represent the lowest symbol values₀ but can represent any of the remaining symbol values s₁, s₂, and s₃.Pre-decision computation block 119 uses the ISI-adjusted voltages V₀ toV₁₁ in this way to populate a look-up table (LUT) relating each voltageregion from R₀ to R₁₂ to a corresponding set of possible symbol valuesand makes these sets available to open-loop stage 125. Second open-loopstage 125 “looks up” the possible values for each region identified byfirst open-loop stage 120 to reduce the four possible PAM-4 symbolvalues to a tentative subset, and thus reduces the computationalcomplexity of selecting a final value for each symbol. For example,second open-loop stage 125(0) can use voltage region R₈ from firstopen-loop stage 120(0) to select tentative-decision set TD₈ for passingto decision stage 110(0), and thus allow stage 110(0) to select finaldecision d₀(k) from among symbol values s₁, s₂, and s₃.

FIG. 4 depicts a tentative-decision look-up table (LUT) 400 relatingvoltage regions R₁₂:R₀ for a current symbol value d_(n)(k) to tentativesymbol values given a preceding symbol value d_(n-1)(k). For eachidentified voltage region R second open-loop stage 125(0) passesdecision stage 110(0) a corresponding tentative decision set TD thatidentifies a set of tentative decisions in relation to the prior symbolvalue. Returning to the example of voltage region R₈, LUT 400 indicatesthat this level corresponds to tentative-decision set TD₈, whichrepresents a current value s₁ if the preceding symbol was s₃, a currentvalue s₂ if the preceding values was s₁ or s₂, and a current value s₃ ifthe preceding value was also s₀. Each set of tentative pre-decisions TDreduces the number of possible symbol values, which eases the timingclosure of decision stage 110. LUT 400 can be static or quasi-static andcan be implemented using either firmware or low-speed logic. LUT 400 canbe shared by all parallel DFE slices in a lane to save area and power.

FIG. 5 details one slice 500 of open-loop equalizer 105 of FIG. 1,including first open-loop stage 120(0) and second open-loop stage125(0). The remaining slices are the same or similar.

First open-loop stage 120(0) includes four comparators 505, 510, 515,and 520 that issue respective partial region decisions r₀, r₁, r₂, andr₃ responsive to a subset of the gamut of reference-voltage levelsV₁₁:V₀. Second open-loop stage 125(0) decodes each combination ofpartial region decisions r₃:r₀ to select among tentative decision setsTD₁₂:TD₀ for a given one of regions R₁₂:R₀, the sets noted for examplein LUT 400 of FIG. 4.

From left to right, comparator 505 compares the level of present symbolx₀(k) with the middle reference-voltage level V₅, issuing logic one(zero) value for partial region decision r₀ if the level of the presentsymbol is above (below) level V₅. Partial region decision r₀ is fed tosecond stage 125(0) and to a multiplexer 525 that compares presentsymbol x₀(k) with either reference-voltage level V₂ or V₈ depending uponthe value of partial region decision r₀ to issue a second partial regiondecision r₁. Two more multiplexers 530 and 535 continue this binarysearch against the remaining reference-voltage levels until the set ofpartial region decision r₃:r₀ indicate one of regions R₁₂:R₀. Secondstage 125(0) then produces the corresponding set of tentative decisionsfrom among sets TD₁₂:TD₀. ISI is thus indirectly compensated for bylocating each symbol's amplitude within an ISI-compensated region.

FIG. 6 is a decision tree 600 illustrating the binary search performedby first open-loop stage 120(0) to identify voltage regions R₁₂:R₀ andthe sets of tentative decisions TD₁₂:TD₀ associated with each region.Each region is shown with four pre-symbol possibilities, one for eachsymbol type, and the corresponding tentative decisions. As notedpreviously, for example, region R₈ represents a current value s₁ if thepreceding symbol was s₃, a current value s₂ if the preceding values wass₁ or s₂, and a current value s₃ if the preceding value was s₀.Temporary decision TD₈ passes a value indicative of these relationshipsto allow decision stage 110 to simply select the final decision d_(n)(k)based on the final decision d_(n-1)(k) for the preceding symbol.

FIG. 7 depicts a tentative-decision LUT 700 similar to LUT of FIG. 4 butincluding a mapping of partial region decisions r₀, r₁, r₂, and r₃ tovoltage regions R₁₂:R₀ and tentative-decision sets TD₁₂:TD₀.

FIG. 8A depicts a second open-loop stage 800 that can be used in placeof open-loop stage 125 of FIG. 1 to produce further refined sets oftentative pre-decisions RTD_(q-1):RTD₀. Second open-loop stage 800includes a first open-loop sub-stage 805 and a second open-loop substage810, each of which is divided into N+1 slices in service oflike-references ones of DFE slices 0 to N in the manner detailed inconnection with FIG. 1.

Sub-stage 805 produces the same sets of tentative pre-decisionsTD_(q-1):TD₀ detailed previously, each set representing the symbol valueor values that are possible for a given voltage region. Sub-stage 810then considers the tentative pre-decisions from neighboring slices, andthus the values of prior symbols, to further reduce the size of one ormore sets of tentative pre-decisions TD_(q-1):TD₀, and thus producerefined sets of tentative pre-decisions RTD_(q-1):RTD₀. Reducing thenumber of potential symbol values further eases timing closure fordecision feedback of e.g. stage 110.

FIG. 8B illustrates how slices of sub-stage 810 of FIG. 8A share sets oftentative pre-decisions TD_(q-1):TD₀ to produce refined sets oftentative pre-decisions RTD_(q-1):RTD₀. A delay element 815 delayspre-decision TD_(N)(k) by one parallel clock cycle to apply delayedpre-decision TD_(N)(k−1) to sub-stage 810(0). Each slice of sub-stage810 receives sets of tentative pre-decisions from an adjacent slice thatrepresent potential values of prior symbol d_(n-1)(k), and that can beused to further reduce the number of tentative symbol values. Withreference to FIG. 7, for example, a slice of sub-stage 810 receivingtentative pre-decisions TD₄ for the present symbol and prior tentativepre-decisions TD₁ from an adjacent slice can pass on a refined set oftentative decisions indicating that the current symbol is either s₁ ors₂. The value so otherwise associated with tentative decision TD₄ iseliminated from consideration because the prior symbol, while notdetermined, is known not to have a value of s₃.

Another embodiment splits the amplitude range illustrated in FIG. 3 intoe.g. four zones, one for each of respective symbol values s₃:s₀ forprocessing in parallel by four instances of the two open-loop stages.Each first open-loop stage considers a reduced number of sub-regions andeach second stage requires a smaller LUT. This embodiment may reduce thelatency of the forward data path, particularly for large numbers of DFEtaps and sub-regions.

While the subject matter has been described in connection with specificembodiments, other embodiments are also envisioned. Therefore, thespirit and scope of the appended claims should not be limited to theforegoing description. Only those claims specifically reciting “meansfor” or “step for” should be construed in the manner required under thesixth paragraph of 35 U.S.C. § 112.

What is claimed is:
 1. A decision-feedback equalizer (DFE) comprising:an input node to receive an input signal expressing a series of symbols,each of the symbols representing one of a set of possible symbol values;a first open-loop stage coupled to the input node to receive the seriesof symbols, the first open-loop stage to compare each symbol in theseries of symbols with a set of reference-voltage levels to identify avoltage region; a second open-loop stage coupled to the first open-loopstage to derive from the voltage region a set of tentative decisionsrepresenting a subset of the set of possible symbol values; and afeedback stage coupled to the second open-loop stage to select one ofthe set of tentative decisions as a final decision responsive to a priorfinal decision; wherein the first open-loop stage selects the set ofreference-voltage levels from a gamut of reference-voltage levelsresponsive to a level of each symbol in the series of symbols; whereinthe comparing of each symbol relative to the set of reference-voltagelevels successively compares the symbol to each reference-voltage levelin the set of reference-voltage levels; and wherein the first open-loopstage performs a binary search for the voltage region by the successivecomparison of the symbol to each reference-voltage level in the set ofreference-voltage levels.
 2. The DFE of claim 1, wherein the firstopen-loop stage, the second open-loop stage, and the feedback stage areof a first DFE slice, the DFE further comprising additional DFE sliceseach coupled to the input node to receive the series of symbols andproduce a respective series of final decisions.
 3. The DFE of claim 2,wherein the feedback stage of each DFE slice receives the prior finaldecision from another of the DFE slices.
 4. The DFE of claim 2, furthercomprising a reference-level generator to generate a gamut ofreference-voltage levels, including the set of reference-voltage levels,and apply the gamut of reference-voltage levels to the first open-loopstage of each of the DFE slices.
 5. The DFE of claim 1, furthercomprising a look-up table, coupled to the second open-loop stage, tostore a mapping between the voltage regions and subsets of the set ofsymbol values.
 6. The DFE of claim 1, the second open-loop stageincluding a substage that further selects the set of tentative decisionsfrom a prior set of tentative decisions.
 7. A decision-feedbackequalizer (DFE) comprising: an input node to receive an input signalexpressing a series of symbols, each of the symbols representing one ofa set of possible symbol values; a reference-level generator to providea gamut of reference-voltage levels; and an open-loop stage coupled tothe input node to receive the series of symbols, the open-loop stage tocompare a present level of each symbol in the series of symbols to asubset of the gamut of reference-voltage levels to identify a voltageregion for the symbol; wherein the open-loop stage selects the subset ofreference-voltage levels responsive to the present level.
 8. The DFE ofclaim 7, wherein comparing the present level of each symbol with thesubset of reference-voltage levels successively compares the presentlevel to each reference-voltage level in the subset of thereference-voltage levels.
 9. The DFE of claim 8, wherein the open-loopstage performs a binary search for the voltage region by the successivecomparing.
 10. The DFE of claim 9, wherein the open-loop stage is of afirst DFE slice, the DFE further comprising additional DFE slices eachcoupled to the input node to receive the series of symbols and samplethe received series of symbols at respective sample timings.
 11. The DFEof claim 10, wherein each of the DFE slices provides a final decision toanother of the DFE slices.
 12. The DFE of claim 7, further comprising: asecond open-loop stage coupled to the first-mentioned open-loop stage toderive from the identified voltage region a set of tentative decisionsrepresenting a subset of the possible symbol values.
 13. The DFE ofclaim 12, further comprising: a feedback stage coupled to the secondopen-loop stage to select one of the tentative decisions as a finaldecision responsive to a prior final decision.
 14. The DFE of claim 12,wherein the second open-loop stage further derives the set of tentativedecisions from a prior set of tentative decisions.
 15. A method ofinterpreting an input signal expressing a series of symbols, each of thesymbols representing one of a set of possible symbol values, the methodcomprising: performing, for each symbol, a binary search for a voltageregion corresponding to the symbol, the binary search comprisingcomparing each symbol in the series of symbols to a set ofreference-voltage levels selected from a gamut of reference-voltagelevels, and wherein the comparing of each symbol performs the binarysearch for the voltage region by sampling the symbol relative to eachreference-voltage level in the set of reference-voltage levels;deriving, from the voltage region, a set of tentative decisionsrepresenting a subset of the possible symbol values; and selecting oneof the tentative decisions as a final decision responsive to a priorfinal decision.
 16. The method of claim 15, wherein the set ofreference-voltage levels is a subset of the gamut of reference-voltagelevels, the method further comprising selecting the subset of the gamutof reference-voltage levels responsive to the comparing.
 17. The methodof claim 15, wherein deriving the set of tentative decisions considers aprior set of tentative decisions.